The present invention relates generally to fabrication of integrated circuits, and more particularly to an improved dicing process.
In the manufacture of semiconductor devices, a plurality of integrated circuits are simultaneously prepared on a semiconductor wafer by conventional semiconductor fabrication techniques. Thus, a wafer can comprise multiple separate integrated circuits formed on a substantially planar surface area of the wafer according to conventional techniques, such as, photolithographic techniques, material deposition techniques, material etching techniques, and material doping techniques to form predetermined patterns and devices on or in a semiconductor body. A plurality of secondary devices such as contact pads, test monitor devices, and devices for measurement and alignment are also provided on the planar surface for the operation, testing and processing of the integrated circuits or other semiconductor devices.
A single integrated circuit is of relatively minute dimensions so that it is convenient to simultaneously form a plurality of circuits on a single wafer while marking the boundaries between the individual devices along substantially perpendicular axes referred to as dicing lines or lanes. Dicing lanes are formed spaced apart in two directions crossing at right angles on a wafer. Generally, the width of the dicing line is about 50-100 microns. As the dicing area is a region generally cut by a saw blade, an element of an integrated circuit is not formed in this region, but a test element for testing the function element or an alignment mark for mask alignment is often formed in the dicing area region.
Current dicing processes include sawing, as well as, scribing and breaking the wafer along the dicing lane. The sawing process is employed with a saw blade coupled to a spindle. The spindle rotates at a high speed to cut the wafer into individual chips. The scribe and break process, on the other hand, comprises dragging a diamond stylus along a surface of a wafer, which creates a stress for fractures to initiate. The wafer is then broken into individual chips. Both processes often cause chipping and the scribe and break process causes non-separation between dies, which results in yield loss. The chips occurring in the substrate propagate rapidly and tend to lead to failures that show up in testing. Currently, such problems are being addressed by providing dicing lanes that are large enough to minimize chipping from extending into active circuit lanes. However, by increasing the size of the dicing lanes, the number of integrated circuits that can be formed on the wafer is limited. Furthermore, the current processes are highly dependent on individual operator skills and are a generally time consuming process.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a semiconductor wafer having improved dicing lanes. The dicing lanes include dry etching or chemically etched grooves formed in a substrate of the wafer. The dry etch or chemically etched grooves can be generally v-shaped. In one aspect of the invention, the dry etch or chemically etched grooves are generally about 0.3 to about 0.5 microns in depth and have a width of about 3 to about 5 microns. However, the depth and width of the grooves and the shape of the grooves can vary depending on the specific implementation. The wafer also includes a plating layer (e.g., gold layer) on a back side of the wafer after wafer is thinned to a specific value and to facilitate bonding of individual circuit chips to a suitable substrate and to effect efficient heat transfer between the chip and the substrate. The plating layer has horizontal and vertical lanes etched in the layer to facilitate breaking of the individual circuit chips from the wafer. The horizontal and vertical lanes etched in the plating layer are coincident to the v-shaped grooves etched in the substrate and/or dicing lanes of the substrate.
The present invention also relates to methods for an improved dicing process and for fabricating a semiconductor wafer with improved dicing lanes. Photolithography and etching processes are employed to etch grooves (e.g., v-shaped grooves) into dicing lanes on a front side of the wafer. A plating layer is then formed on a back side of the wafer and is subsequently etched to form lanes coincident with the grooves and/or dicing lanes on the front side of the wafer. The wafer can then be broken into individual circuit chips by applying stress to the back of the wafer, such that the wafer cleanly breaks along the lanes and v-shaped grooves.
To the accomplishment of the foregoing and related ends, certain illustrative aspects of the invention are described herein in connection with the following description and the annexed drawings. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such aspects and their equivalents. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.